View PIC18F8490_253162.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PIC18F6390/6490/8390/8490
PIC18F6390/6490/8390/8490 Rev. B3 Silicon Errata
The PIC18F6390/6490/8390/8490 Rev. B3 parts you have received conform functionally to the Device Data Sheet (DS39629), except for the anomalies described below. Any Data Sheet Clarification issues related to the PIC18F6390/6490/8390/8490 will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues. All of the issues listed here will be addressed in future revisions of the PIC18F6390/6490/8390/8490 silicon. The following silicon errata apply only to PIC18F6390/6490/8390/8490 devices with these Device/Revision IDs: Part Number PIC18F6390 PIC18F6490 PIC18F8390 PIC18F8490 Device ID 00 1011 101 00 0110 101 00 1101 100 00 0110 100 Revision ID 00011 00011 00011 00011
1. Module: MSSP
In its current implementation, the I2CTM Master mode operates as follows: a) The Baud Rate Generator for I2C in Master mode is slower than the rates specified in Table 15-3 of the Device Data Sheet. For this revision of silicon, use the values shown in Table 1 in place of those shown in Table 15-3 of the Device Data Sheet. The differences are shown in bold text. b) Use the following formula in place of the one shown in Register 15-4 (SSPCON1) of the Device Data Sheet for bit description SSPM3:SSPM0 = 1000. SSPADD = INT((FCY/FSCL) - (FCY/1.111 MHz)) - 1 Date Codes that pertain to this issue: All engineering and production devices.
The Device IDs (DEVID1 and DEVID2) are located at addresses 3FFFFEh:3FFFFFh in the device's configuration space. They are shown in hexadecimal in the format "DEVID2 DEVID1".
TABLE 1:
FOSC 40 MHz 40 MHz 40 MHz 16 MHz 16 MHz 16 MHz 4 MHz 4 MHz 4 MHz Note 1:
I2CTM CLOCK RATE w/BRG
FCY 10 MHz 10 MHz 10 MHz 4 MHz 4 MHz 4 MHz 1 MHz 1 MHz 1 MHz FCY * 2 20 MHz 20 MHz 20 MHz 8 MHz 8 MHz 8 MHz 2 MHz 2 MHz 2 MHz BRG Value 0Eh 15h 59h 05h 08h 23h 01h 08h 00h FSCL (2 Rollovers of BRG) 400 kHz(1) 312.5 kHz 100 kHz 400 kHz(1) 308 kHz 100 kHz 333 kHz(1) 100 kHz 1 MHz(1)
The I2CTM interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application.
(c) 2005 Microchip Technology Inc.
DS80207B-page 1
PIC18F6390/6490/8390/8490
2. Module: MSSP
When the MSSP is configured for SPITM Master mode, the SDO pin cannot be disabled by setting the TRISC<5> bit. The SDO pin always outputs the content of SSPBUF regardless of the state of the TRIS bit. In Slave mode with Slave Select enabled, SSPM3:SSPM0 = 0010 (SSPCON1<3:0>), the SDO pin can be disabled by placing a logic high level on the SS pin (RF7). Work around None. Date Codes that pertain to this issue: All engineering and production devices.
4. Module: MSSP
In 10-bit Addressing mode, when a Repeated Start is issued followed by the high address byte and a write command (R/W = 0), an ACK is not issued. Work around There are two work arounds available: 1. Single-Master Environment: In a single-master environment, the user must issue a Stop, then a Start, followed by a write to the address high, then the address low followed by the data. 2. Multi-Master Environment: In a multi-master environment, the user must issue a Repeated Start, send a dummy write command to a different address, issue another Repeated Start and then send a write to the original address. This procedure will prevent loss of the bus. Date Codes that pertain to this issue: All engineering and production devices.
3. Module: MSSP
After an I2C transfer is initiated, the SSPBUF register may be written for up to 10 TCY before additional writes are blocked. The data transfer may be corrupted if SSPBUF is written during this time. The WCOL bit is set any time an SSPBUF write occurs during a transfer. Work around Avoid writing SSPBUF until the data transfer is complete, indicated by the setting of the SSPIF bit (PIR1<3>). Verify the WCOL bit (SSPCON1<7>) is clear after writing SSPBUF to ensure any potential transfer in progress is not corrupted. Date Codes that pertain to this issue: All engineering and production devices.
5. Module: MSSP
I2C Receive mode should be enabled (i.e., RCEN bit should be set) only when the system is idle (i.e., when ACKEN, RCEN, PEN, RSEN and SEN all equal zero). It should not be possible to set the RCEN bit when the system is not idle, however, the RCEN bit can be set under this circumstance. Work around Wait for the system to become idle before setting the RCEN bit. This requires a check for the following bits to be clear: ACKEN, RCEN, PEN, RSEN and SEN. Date Codes that pertain to this issue: All engineering and production devices.
DS80207B-page 2
(c) 2005 Microchip Technology Inc.
PIC18F6390/6490/8390/8490
6. Module: CCP
When operating either Timer1 or Timer3 as a counter with a prescale value other than 1:1 and operating the CCP in Compare mode with the Special Event Trigger (CCP1CON bits CCP1M3:CCP1M0 = 1011), the Special Event Trigger Reset of the timer occurs as soon as there is a match between TMRxH:TMRxL and CCPR1H:CCPR1L. This differs from the PIC18F452, where the Special Event Trigger Reset of the timer occurs on the next prescaler output pulse after the match between TMRxH:TMRxL and CCPR1H:CCPR1L. Work around To achieve the same timer Reset period on the PIC18F8490 family as the PIC18F452 family for a given clock source, add 1 to the value in CCPR1H:CCPR1L. In other words, if CCPR1H:CCPR1L = x for the PIC18F452, to achieve the same Reset period on the PIC18F8490 family, CCPR1H:CCPR1L = x + 1, where the prescale is 1, 2, 4 or 8 depending on the T1CKPS1:T1CKPS0 bit values. Date Codes that pertain to this issue: All engineering and production devices.
7. Module: CCP
The CCP1 and CCP2, configured for PWM mode with 1:1 Timer2 prescaler and duty cycle set to the period minus 1, may result in the PWM output(s) remaining at a logic low level. Clearing the PR2 register to select the fastest period may also result in the output(s) remaining at a logic low output level. Work around To ensure a reliable waveform, verify that the selected duty cycle does not equal the 10-bit period minus 1 prior to writing these locations, or use 1:4 or 1:16 Timer2 prescale. Also, verify the PR2 register is not written to 00h. All other duty cycle and period settings will function as described in the Device Data Sheet. The CCP modules remain capable of 10-bit accuracy. Date Codes that pertain to this issue: All engineering and production devices.
(c) 2005 Microchip Technology Inc.
DS80207B-page 3
PIC18F6390/6490/8390/8490
8. Module: A/D
The A/D offset is greater than the specified limit in Table 26-23 of the Device Data Sheet. The addition of Parameter A06A and updated conditions and limits are shown in bold text in Table 2. Work around Three work arounds exist. 1. Configure the A/D to use the VREF+ and VREFpins for the voltage references. This is done by setting the VCFG<1:0> bits (ADCON1<5:4>). 2. Perform a conversion on a known voltage reference voltage and adjust the A/D result in software. 3. Increase system clock speed to 40 MHz and adjust A/D settings accordingly. Higher system clock frequencies decrease offset error.
TABLE 2:
A/D CONVERTER CHARACTERISTICS: PIC18F6390/6490/8390/8490 (INDUSTRIAL) PIC18LF6390/6490/8390/8490 (INDUSTRIAL)
Characteristic Offset Error Offset Error Min -- -- Typ -- -- Max <1.5 <3.5 Units LSb LSb Conditions VREF = VREF+ and VREFVREF = VSS and VDD
Param Symbol No. A06A A06 EOFF EOFF
Date Codes that pertain to this issue: All engineering and production devices.
9. Module: BOD
The BOD module may reset below the minimum operating voltage of the device when configured for BORV1:BORV0 = 11. The updated Reset voltage specifications are shown in bold in Table 3.
10. Module: EUSART
When performing back-to-back transmission in 9-bit mode (TX9D bit in the TXSTAx register is set), an ongoing transmission's timing can be corrupted if the TX9D bit (for the next transmission) is not written immediately following the setting of TXxIF. This is because any write to the TXSTAx register results in a reset of the Baud Rate Generator which will effect any ongoing transmission. Work around Load TX9D just after TXxIF is set, either by polling TXxIF or by writing TX9D at the beginning of the Interrupt Service Routine, or only write to TX9D when a transmission is not in progress (TRMT = 1). Date Codes that pertain to this issue: All engineering and production devices.
TABLE 3:
Param Sym No. D005
BROWN-OUT RESET VOLTAGE
Characteristic Min Typ Max Unit
VBOR Brown-out Reset Voltage PIC18LF6390/6490/8390/8490 BORV1:BORV0 = 11 N/A 2.05 N/A V
Work around Use the next higher BOD voltage setting to ensure a low VDD is detected above 2.0V. Date Codes that pertain to this issue: All engineering and production devices.
DS80207B-page 4
(c) 2005 Microchip Technology Inc.
PIC18F6390/6490/8390/8490
11. Module: EUSART
When performing back-to-back transmission in 9-bit mode (TX9D bit in the TXSTAx register is set), the second byte may be corrupted if it is written into TXREGx immediately after the TMRT bit is set. Work around Execute a software delay, at least one-half the transmission's bit time, after TMRT is set and prior to writing subsequent bytes into TXREGx. Date Codes that pertain to this issue: All engineering and production devices.
14. Module: Timer1/Timer3
When Timer1 or Timer3 is in External Clock Synchronized mode and the external clock period is between 1 and 2 TCY, interrupts will occasionally be skipped. Work around Avoid using an external clock with a period (1/ frequency) between 1 and 2 TCY. Date Codes that pertain to this issue: All engineering and production devices.
12. Module: AUSART
The AUSART for PIC18F6390/6490/8390/8490 devices may not recognize a received Stop bit if the combined error rate is too high. Work around 1. Increase the baud rate of the device by decrementing the SPBRGHx:SPBRGx register pair value by one. Verify that the new baud rate does not exceed the maximum combined error rate of the application. 2. Configure the transmitter to send two Stop bits. Date Codes that pertain to this issue: All engineering and production devices.
15. Module: Timer1/Timer3
When Timer1/Timer3 is operating in 16-bit mode and the prescale setting is not 1:1, a write to the TMR1H/TMR3H Buffer registers may lengthen the duration of the period between the increments of the timer for the period in which TMR1H/TMR3H was written. Work around Two work arounds are available: 1) Stop Timer1/ Timer3 before writing the TMR1H/TMR3H registers; 2) Write TMR1L/TMR3L immediately after writing TMR1H/TMR3H. Date Codes that pertain to this issue: All engineering and production devices.
13. Module: Timer1/Timer3
When Timer1 or Timer3 is configured for external clock source and the CCPxCON register is configured with 0x0B (Compare mode, trigger special event), the timer is not reset on a Special Event Trigger. Work around Modify firmware to reset the Timer1/Timer3 registers upon detection of the compare match condition -- TMRxL and TMRxH. Date Codes that pertain to this issue: All engineering and production devices.
(c) 2005 Microchip Technology Inc.
DS80207B-page 5
PIC18F6390/6490/8390/8490
16. Module: Interrupts
If an interrupt occurs during a two-cycle instruction that modifies the STATUS, BSR or WREG register, the unmodified value of the register will be saved to the corresponding Fast Return (Shadow) register and upon a fast return from the interrupt, the unmodified value will be restored to the STATUS, BSR or WREG register. For example, if a high priority interrupt occurs during the instruction, MOVFF TEMP, WREG, the MOVFF instruction will be completed and WREG will be loaded with the value of TEMP before branching to ISR. However, the previous value of WREG will be saved to the Fast Return register during ISR branching. Upon return from the interrupt with a fast return, the previous value of WREG in the Fast Return register will be written to WREG. This results in WREG containing the value it had before execution of MOVFF TEMP, WREG. Affected instructions are: MOVFF Fs, Fd where Fd is WREG, BSR or STATUS; MOVSF Zs, Fd where Fd is WREG, BSR or STATUS; and MOVSS [Zs], [Zd] where the destination is WREG, BSR or STATUS. Work around 1. Assembly Language Programming: If any twocycle instruction is used to modify the WREG, BSR or STATUS register, do not use the RETFIE FAST instruction to return from the interrupt. Instead, save/restore WREG, BSR and STATUS via software per Example 8-1 in the Device Data Sheet. Alternatively, in the case of MOVFF, use the MOVF instruction to write to WREG instead. For example, use: MOVF TEMP, W MOVWF BSR instead of MOVFF TEMP, BSR. 2. C Language Programming: The exact work around depends on the compiler in use. Please refer to your C compiler documentation for details. If using the Microchip MPLAB(R) C18 C Compiler, define both high and low priority interrupt handler functions as "low priority" by using the pragma interruptlow directive. This directive instructs the compiler to not use the RETFIE FAST instruction. If the proper high priority interrupt bit is set in the IPRx register, then the interrupt is treated as high priority in spite of the pragma interruptlow directive. The following code snippet demonstrates the work around using the C18 compiler: Date Codes that pertain to this issue: All engineering and production devices. #pragma interruptlow MyLowISR void MyLowISR(void) { // Handle low priority interrupts. } // Although MyHighISR is a high priority interrupt, use interruptlow pragma so that // the compiler will not use retfie FAST. #pragma interruptlow MyHighISR void MyHighISR(void) { // Handle high priority interrupts. } #pragma code highVector=0x08 void HighVector (void) { _asm goto MyHighISR _endasm } #pragma code /* return to default code section */ #pragma code lowVector=0x18 void LowVector (void) { _asm goto MyLowISR _endasm } #pragma code /* return to default code section */
DS80207B-page 6
(c) 2005 Microchip Technology Inc.
PIC18F6390/6490/8390/8490
REVISION HISTORY
Rev A Document (8/2004) First revision of this document which includes silicon issues 1-4 (MSSP), 5 (PWM), 6 (CCP), 7 (A/D), 8 (AUSART), 9 (Timer1/Timer3), 10 (Timer1) and 11 (LCD). Rev B Document (2/2005) Removed previous issue 11 (LCD). Added Date Code information for all issues and updated text in issues 1, 3, 4 and 5 (MSSP), 12 (AUSART), 14 (Timer1/Timer3) and added issues 6 (CCP), 9 (BOD), 10-11 (EUSART), 15 (Timer1/Timer3) and 16 (Interrupts).
(c) 2005 Microchip Technology Inc.
DS80207B-page 7
PIC18F6390/6490/8390/8490
NOTES:
DS80207B-page 8
(c) 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2005 Microchip Technology Inc.
DS80207B-page 9
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westford, MA Tel: 978-692-3848 Fax: 978-692-3821 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Qingdao Tel: 86-532-502-7355 Fax: 86-532-502-7205
ASIA/PACIFIC
India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 Japan - Kanagawa Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459
EUROPE
Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 France - Massy Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Ismaning Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 England - Berkshire Tel: 44-118-921-5869 Fax: 44-118-921-5820
10/20/04
DS80207B-page 10
(c) 2005 Microchip Technology Inc.

▲Up To Search▲

Price & Availability of PIC18F8490

	To Download PIC18F8490 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .